A Novel and Fast Hardware Implementation for Golay Code Encoder

نویسندگان
چکیده

برای دانلود رایگان متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

A Novel and Efficient Hardware Implementation of Scalar Point Multiplier

A new and highly efficient architecture for elliptic curve scalar point multiplication is presented. To achieve the maximum architectural and timing improvements we have reorganized and reordered the critical path of the Lopez-Dahab scalar point multiplication architecture such that logic structures are implemented in parallel and operations in the critical path are diverted to noncritical path...

متن کامل

Novel Hardware Implementation for Fast Address Lookups

The major bottleneck in the performance of routers is the address lookup for determining the next hop address. The problem of determining the next hop is made more complicated by the fact that routers store variable length prefixes in the forwarding tables. This paper describes a new hardware algorithm that gives a fast and efficient solution for address lookups. As implemented in the forwardin...

متن کامل

Hardware Implementation of wavelet based Image encoder

ABSTRACT Although FPGA technology offers the potential of designing high performance systems at low cost, its programming model is prohibitively low level. To allow a novice signal/image processing end-user to benefit from this kind of devices, the level of design abstraction needs to be raised. This approach will help the application developer to focus on signal/image processing algorithms rat...

متن کامل

Hardware Implementation for Fast Convolution with a PN Code Using Field Programmable Gate Array

In code division multiple access (CDMA) system, receivers spend long time to acquire the signals. This is mostly due to the use of expensive FFT-based convolvers in the acquisition process. This paper shows a substitute algorithm for calculating the convolution that requires less computation time. The algorithm uses Walsh transform instead of FFTs. FFTbased algorithm requires 2 FFTs and one IFF...

متن کامل

FPGA Implementation of Cyclic Code Encoder and Decoder

This paper presents Cyclic code Encoder and Decoder with its soft core design as well hardware implementation on FPGA. The design includes both encoder and decoder part that can be used in a communication system for encoding a message at the transmitter and decoding it, detecting error and correcting it on the receiver part. The source code for Encoder and Decoder has been formulated in VHDL ( ...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

ژورنال

عنوان ژورنال: Advances in Electrical and Electronic Engineering

سال: 2018

ISSN: 1804-3119,1336-1376

DOI: 10.15598/aeee.v16i4.2735